0510 clockCounter, upCounter

clockCounter.v

`timescale 1ns / 1ps

module clock(
    input clk,
    input reset,
    output [3:0] fndCom,
    output [7:0] fndFont
);

wire w_clk_1s, w_clk_s;
wire [13:0] w_count_m_digit;
wire [5:0] w_clk_60s, w_clk_60m;

clkDiv #(.MAX_COUNT(100_000_000)) U_ClkDiv_1s (
        .clk  (clk),
        .reset(reset),
        .o_clk(w_clk_1s)
);

counter #(.MAX_COUNT(60)) U_Counter_s (
        .clk  (w_clk_1s),
        .reset(reset),
        .count(w_clk_60s),
        .o_min_clk(w_clk_s)
);

counter #(.MAX_COUNT(60)) U_Counter_m (
        .clk  (w_clk_s),
        .reset(reset),
        .count(w_clk_60m)
);

fndController U_FndController(
    .clk(clk),
    .reset(reset),
    .digit(w_clk_60s),
    .digitm(w_clk_60m),
    .fndFont(fndFont),
    .fndCom(fndCom)
);

endmodule

 

fndController.v

`timescale 1ns / 1ps

module fndController (
    input         clk,
    input         reset,
    input  [13:0] digit,
    input  [13:0] digitm,
    output [ 7:0] fndFont,
    output [ 3:0] fndCom
    );

    wire [3:0] w_digit_1, w_digit_10, w_digit_100, w_digit_1000;
    wire [3:0] w_digitm_1, w_digitm_10, w_digitm_100, w_digitm_1000;
    wire [3:0] w_digit;
    wire [1:0] w_count;
    wire w_clk_1khz;

    clkDiv #(.MAX_COUNT(100_000)) U_ClkDiv( // (100_000)이 없으면 default
        .clk(clk),
        .reset(reset),
        .o_clk(w_clk_1khz)
    );

    counter #(.MAX_COUNT(4)) U_Counter_2bit(
        .clk(w_clk_1khz),
        .reset(reset),
        .count(w_count),
        .o_min_clk()
    );

    Decoder U_Decoder_2x4 (
        .x(w_count),
        .y(fndCom)
    );

    digitSplitter U_DigitSplitter (
        .i_digit(digit),
        .o_digit_1(w_digit_1),
        .o_digit_10(w_digit_10),
        .o_digit_100(w_digit_100),
        .o_digit_1000(w_digit_1000)
    );

    digitSplitter U_DigitSplitter_m (
        .i_digit(digitm),
        .o_digit_1(w_digitm_1),
        .o_digit_10(w_digitm_10),
        .o_digit_100(w_digitm_100),
        .o_digit_1000(w_digitm_1000)
    );

    Mux U_Mux (
        .sel(w_count),
        .x0 (w_digit_1),
        .x1 (w_digit_10),
        .x2 (w_digitm_1),
        .x3 (w_digitm_10),
        .y  (w_digit)
    );

    BCDtoSEG U_BcdToSeg0 (
        .bcd(w_digit),
        .seg(fndFont)
    );

endmodule


module Decoder (
    input      [1:0] x,
    output reg [3:0] y
);

    always @(x) begin
        case (x)
            2'h0: y = 4'b1110;
            2'h1: y = 4'b1101;
            2'h2: y = 4'b1011;
            2'h3: y = 4'b0111;
            default: y = 4'b1110;
        endcase
    end

endmodule

module digitSplitter (
    input  [13:0] i_digit,
    output [ 3:0] o_digit_1,
    output [ 3:0] o_digit_10,
    output [ 3:0] o_digit_100,
    output [ 3:0] o_digit_1000
);

    assign o_digit_1 = i_digit % 10;
    assign o_digit_10 = i_digit / 10 % 6;
    assign o_digit_100 = i_digit / 60 % 10;
    assign o_digit_1000 = i_digit / 600 % 6;

endmodule

module Mux (
    input      [1:0] sel,
    input      [3:0] x0,
    input      [3:0] x1,
    input      [3:0] x2,
    input      [3:0] x3,
    output reg [3:0] y
);

    always @(sel, x0, x1, x2, x3) begin
        case (sel)
            2'b00:   y = x0;
            2'b01:   y = x1;
            2'b10:   y = x2;
            2'b11:   y = x3;
            default: y = x0;
        endcase
    end

endmodule

module BCDtoSEG (
    input      [3:0] bcd,
    output reg [7:0] seg
);

    always @(bcd) begin  // bcd 변화가 감지되면 실행
        case (bcd)
            4'h0: seg = 8'hc0;
            4'h1: seg = 8'hf9;
            4'h2: seg = 8'ha4;
            4'h3: seg = 8'hb0;
            4'h4: seg = 8'h99;
            4'h5: seg = 8'h92;
            4'h6: seg = 8'h82;
            4'h7: seg = 8'hf8;
            4'h8: seg = 8'h80;
            4'h9: seg = 8'h90;
            4'ha: seg = 8'h88;
            4'hb: seg = 8'h83;
            4'hc: seg = 8'hc6;
            4'hd: seg = 8'ha1;
            4'he: seg = 8'h86;
            4'hf: seg = 8'h8e;
            default: seg = 8'hff;
        endcase
    end

endmodule

module counter #(parameter MAX_COUNT = 4)(
    input  clk,
    input reset,
    output [$clog2(MAX_COUNT)-1:0]  count,
    output o_min_clk
);

    reg [$clog2(MAX_COUNT)-1:0] counter = 0;
    reg r_tick = 0;

    assign count = counter; // wire은 assign으로 연결해야함.
    assign o_min_clk = r_tick;

    always @(posedge clk, posedge reset) begin  // 비동기 reset
        if (reset == 1'b1) begin
            counter <= 0;
        end
        else begin
            if (counter == MAX_COUNT - 1) begin
                counter <= 0;
                r_tick <= 1'b1;
            end
            else begin
                counter <= counter + 1;
                r_tick <= 1'b0;
            end
        end
    end

endmodule

module clkDiv #(parameter MAX_COUNT = 100)(
    input clk,
    input reset,
    output o_clk
);
    reg [$clog2(MAX_COUNT)-1:0] counter = 0;  // [16:0]으로 만들어줌. $clog2 : log2()
    reg r_tick = 0 ;

    assign o_clk = r_tick;

    always @(posedge clk, posedge reset) begin
        if (reset) begin
            counter <= 0;
        end
        else begin
            if (counter == (MAX_COUNT - 1)) begin
                counter <= 0;
                r_tick <= 1'b1;
            end
            else begin
                counter <= counter + 1;
                r_tick <= 1'b0;
            end
        end
    end
    
endmodule

 

schematic

constraint

 

video

 

---

---

upCounter

 

upCounter_10k

`timescale 1ns / 1ps

module UpCounter_10k(
    input clk,
    input reset,
    output[3:0] fndCom,
    output[7:0] fndFont
    );

    wire w_clk_10hz;
    wire [13:0] w_count_10k;

    clkDiv #(.MAX_COUNT(10_000_000)) U_ClkDiv_10Hz(
        .clk(clk),
        .reset(reset),
        .o_clk(w_clk_10hz)
    );

    counter #(.MAX_COUNT(10_000)) U_Counter_10k(
        .clk(w_clk_10hz),
        .reset(reset),
        .count(w_count_10k)
    );

    fndController U_FndController(
        .clk(clk),
        .reset(reset),
        .digit(w_count_10k),
        .fndFont(fndFont),
        .fndCom(fndCom)
    );

endmodule

 

 

fndController.v

`timescale 1ns / 1ps

module fndController (
    input         clk,
    input         reset,
    input  [13:0] digit,
    output [ 7:0] fndFont,
    output [ 3:0] fndCom
    );

    wire [3:0] w_digit_1, w_digit_10, w_digit_100, w_digit_1000;
    wire [3:0] w_digit;
    wire [1:0] w_count;
    wire w_clk_1khz;

    clkDiv #(.MAX_COUNT(100_000)) U_ClkDiv( // (100_000)이 없으면 default
        .clk(clk),
        .reset(reset),
        .o_clk(w_clk_1khz)
    );

    counter #(.MAX_COUNT(4)) U_Counter_2bit(
        .clk(w_clk_1khz),
        .reset(reset),
        .count(w_count)
    );

    Decoder U_Decoder_2x4 (
        .x(w_count),
        .y(fndCom)
    );

    digitSplitter U_DigitSplitter (
        .i_digit(digit),
        .o_digit_1(w_digit_1),
        .o_digit_10(w_digit_10),
        .o_digit_100(w_digit_100),
        .o_digit_1000(w_digit_1000)
    );

    Mux U_Mux (
        .sel(w_count),
        .x0 (w_digit_1),
        .x1 (w_digit_10),
        .x2 (w_digit_100),
        .x3 (w_digit_1000),
        .y  (w_digit)
    );

    BCDtoSEG U_BcdToSeg0 (
        .bcd(w_digit),
        .seg(fndFont)
    );

endmodule


module Decoder (
    input      [1:0] x,
    output reg [3:0] y
);

    always @(x) begin
        case (x)
            2'h0: y = 4'b1110;
            2'h1: y = 4'b1101;
            2'h2: y = 4'b1011;
            2'h3: y = 4'b0111;
            default: y = 4'b1110;
        endcase
    end

endmodule

module digitSplitter (
    input  [13:0] i_digit,
    output [ 3:0] o_digit_1,
    output [ 3:0] o_digit_10,
    output [ 3:0] o_digit_100,
    output [ 3:0] o_digit_1000
);

    assign o_digit_1 = i_digit % 10;
    assign o_digit_10 = i_digit / 10 % 10;
    assign o_digit_100 = i_digit / 100 % 10;
    assign o_digit_1000 = i_digit / 1000 % 10;

endmodule

module Mux (
    input      [1:0] sel,
    input      [3:0] x0,
    input      [3:0] x1,
    input      [3:0] x2,
    input      [3:0] x3,
    output reg [3:0] y
);

    always @(sel, x0, x1, x2, x3) begin
        case (sel)
            2'b00:   y = x0;
            2'b01:   y = x1;
            2'b10:   y = x2;
            2'b11:   y = x3;
            default: y = x0;
        endcase
    end

endmodule

module BCDtoSEG (
    input      [3:0] bcd,
    output reg [7:0] seg
);

    always @(bcd) begin  // bcd 변화가 감지되면 실행
        case (bcd)
            4'h0: seg = 8'hc0;
            4'h1: seg = 8'hf9;
            4'h2: seg = 8'ha4;
            4'h3: seg = 8'hb0;
            4'h4: seg = 8'h99;
            4'h5: seg = 8'h92;
            4'h6: seg = 8'h82;
            4'h7: seg = 8'hf8;
            4'h8: seg = 8'h80;
            4'h9: seg = 8'h90;
            4'ha: seg = 8'h88;
            4'hb: seg = 8'h83;
            4'hc: seg = 8'hc6;
            4'hd: seg = 8'ha1;
            4'he: seg = 8'h86;
            4'hf: seg = 8'h8e;
            default: seg = 8'hff;
        endcase
    end

endmodule

module counter #(parameter MAX_COUNT = 4)(
    input  clk,
    input reset,
    output [$clog2(MAX_COUNT)-1:0]  count
);

    reg [$clog2(MAX_COUNT)-1:0] counter = 0;
    assign count = counter; // wire은 assign으로 연결해야함.

    always @(posedge clk, posedge reset) begin  // 비동기 reset
        if (reset == 1'b1) begin
            counter <= 0;
        end
        else begin
            if (counter == MAX_COUNT - 1) begin
                counter <= 0;
            end
            else begin
                counter <= counter + 1;
            end
        end
    end

endmodule

module clkDiv #(parameter MAX_COUNT = 100)(
    input clk,
    input reset,
    output o_clk
);
    reg [$clog2(MAX_COUNT)-1:0] counter = 0;  // [16:0]으로 만들어줌. $clog2 : log2()
    reg r_tick = 0 ;

    assign o_clk = r_tick;

    always @(posedge clk, posedge reset) begin
        if (reset) begin
            counter <= 0;
        end
        else begin
            if (counter == (MAX_COUNT - 1)) begin
                counter <= 0;
                r_tick <= 1'b1;
            end
            else begin
                counter <= counter + 1;
                r_tick <= 1'b0;
            end
        end
    end
    
endmodule

 

schematic

 

constraint

 

video